This invention generally relates to network processing; more particularly; the invention aims at providing an implementation to allow access to an external coprocessor by a parser and other processors from a same network processor.
High performance network processors on one chip may have to handle sophisticated network functions. Particularly a packet parser, for instance in an Ethernet adapter, may have to support high level packet classification and packet filtering functions which cannot be all handled on a chip. In these circumstances, the parser will have to kick-off some packet processing functions to an external coprocessor and get in return the result from the coprocessor in order to use it as an input to its own packet process result.
It is common to decide for externalizing network processing functions from the packet parser because different functions may require different processing architecture and performance, the network processor chip being not able to include all these characteristics. The other good reason is an area limitation problem on the chip as packet parsing additional network function may require logic and arrays which may be very large.
A typical additional network processing function which may be externalized by the packet parser to the coprocessor is packet classification including, as an example, a lookup in a ternary content addressable memory (TCAM) or a hash-based lookup for which different search algorithm are employed (Patricia tree, Cuckoo algorithm etc.). One other function which can be externalized by the packet parser to the coprocessor is the packet filtering functions which are based on recognition of patterns extracted from the packet.
When other processors in the network processor need also to externalize software functions towards the same external coprocessor as the per-port parser in the network adapter of the network processor a physical connection to the external coprocessor needs to be added inside the network processor to allow to support this additional ‘software path’. As the processors are connected to the internal bus, an implementation of a physical connection for software path would comprise a bus interface unit and bi-directional serialized lines towards the external coprocessor. This additional implementation may become very costly in terms of silicon area in a single chip network processor.
The U.S. Pat. No. 7,428,618 relates to a network node structure architected around two Net Processors, one for each direction of packet streams, communicating through a shared memory. The structure is complemented with a set of coprocessors located on a daughter card. All coprocessors are interconnected via hardware Control Logic which also provides an interface to one of the two Net Processors, via a dedicated memory. In this prior art document, there is no description of a mixed type of interface needed between the network processor and the external coprocessor. The externalization of processing functions to the external coprocessor is rather based on single requestor (a Net processor) that can dispatch requests to multiple coprocessors. This is opposed to the architecture in which the coprocessor requestors are a parser module and software entities.